`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:42:49 10/24/2013
// Design Name:   pseudoRandomInterrupter
// Module Name:   /home/andy/Documents/uofa-mips/trunk/BoardSystem_trunk/src/controllers/math/pseudoRandomInterrupter_test.v
// Project Name:  nexys2_1200_audio_project
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: pseudoRandomInterrupter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module pseudoRandomInterrupter_test;

	// Inputs
	reg clk;
	reg reset;
	reg enable;
	reg [3:0] address;
	reg [31:0] dataIn;
	reg write;

	// Outputs
	wire [31:0] dataOut;
	wire done;
	wire interrupt;

	// Instantiate the Unit Under Test (UUT)
	pseudoRandomInterrupter uut (
		.clk(clk), 
		.reset(reset), 
		.enable(enable), 
		.address(address), 
		.dataIn(dataIn), 
		.dataOut(dataOut), 
		.write(write), 
		.done(done), 
		.interrupt(interrupt)
	);

	always
	begin
		clk = 1;
		#10;
		clk = 0;
		#10;
	end
	
	initial begin
		// Initialize Inputs
		reset = 1;
		enable = 0;
		address = 0;
		dataIn = 0;
		write = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		reset = 0;
		dataIn = 555555555;
		write = 1;
		enable = 1;
		
		#20;
		
		enable = 0;
		write = 0;
		
		#300;
        
		// Add stimulus here

	end
      
endmodule

